Index: uhci_pci.c
===================================================================
RCS file: /usr/CVS-Repository/src/sys/pci/uhci_pci.c,v
retrieving revision 1.26.2.4
diff -u -r1.26.2.4 uhci_pci.c
--- uhci_pci.c	15 Aug 2001 17:03:08 -0000	1.26.2.4
+++ uhci_pci.c	22 Feb 2002 08:55:18 -0000
@@ -125,8 +125,13 @@
 uhci_pci_resume(device_t self)
 {
 	uhci_softc_t *sc = device_get_softc(self);
+	u_int32_t csr;
 
 	uhci_power(PWR_RESUME, sc);
+	/* Enable the device. */
+	csr = pci_read_config(self, PCI_COMMAND_STATUS_REG, 4);
+	pci_write_config(self, PCI_COMMAND_STATUS_REG, 
+		csr | PCIM_CMD_BUSMASTEREN, 4);
 	bus_generic_resume(self);
 
 	return 0;
@@ -182,6 +187,7 @@
 	uhci_softc_t *sc = device_get_softc(self);
 	int rid;
 	int err;
+	u_int32_t csr;
 
 	rid = PCI_UHCI_BASE_REG;
 	sc->io_res = bus_alloc_resource(self, SYS_RES_IOPORT, &rid,
@@ -275,6 +281,11 @@
 		uhci_pci_detach(self);
 		return ENXIO;
 	}
+
+	/* Enable the device. */
+	csr = pci_read_config(self, PCI_COMMAND_STATUS_REG, 4);
+	pci_write_config(self, PCI_COMMAND_STATUS_REG, 
+		csr | PCIM_CMD_BUSMASTEREN, 4);
 
 	/* Set the PIRQD enable bit and switch off all the others. We don't
 	 * want legacy support to interfere with us